1. Field of the Invention
The present disclosure relates generally to semiconductor fabrication, and more particularly to ion implantation processes during semiconductor fabrication.
2. Description of the Related Art
Semiconductor-on-insulator (SOI) structures have advantages over conventional bulk substrates such as elimination of latch-up, reduced short-channel effects, improved radiation hardness, and dynamic coupling, among others. Because of these advantages, semiconductor device manufacturers commonly form metal-oxide semiconductor field effect transistors (MOSFETs) on SOI structures.
In a typical MOSFET, a source and a drain are formed in an active semiconductor region by implanting N-type or P-type impurities in the layer of semiconductor material. Between the source and the drain is a channel (or body) region, above which is a gate electrode. Unfortunately, MOSFETs formed on SOI structures often experienced a floating body effect (FBE), which lead to the development of tied-body construction techniques, particularly in the manufacture of partially-depleted SOI devices such as the t-type or “hammer head” gate electrode seen in FIG. 1.
FIG. 1 illustrates a top view of a typical t-type gate transistor 100 according to the prior art. This t-type gate transistor is also known as a “hammerhead” transistor, because the shape of the block of the polysilicon portion 10 between the gate 9 and the contact 3 in region 4 resembles a hammerhead. Transistor 100 is formed in an active area having a first region 2, having a first width, and a second region 4, having a second width. Contacts 3 are located in the region 2 and contact 5 is formed in region 4. Another view of t-type gate transistor 100 is shown in FIG. 2.
FIG. 2 illustrates a cross-sectional view of t-type transistor 100 Line A of FIG. 1, while FIG. 3 illustrates a more detailed plan view of a portion of transistor 100. Line A is a cross-section just inside the gate 9 sidewall. This cross-section results in the source/drain (S/D) extensions 8 and halo implants 6 underlying the edge of the gate 9 being shown. From FIG. 2, it is seen that transistor 100 utilizes partially depleted SOI manufacturing technology. Components in FIG. 2 not illustrated in FIG. 1 include isolation structures 18, insulator layer 11, substrate 12, dielectric layer 17, source/drain (S/D) extension 8 underlying the gate 9, and halo implant 6, underlying the gate 9.
While tied-body transistors such as t-type transistor 100 avoid FBE problems by tying the transistor body to a contact CMOS scaling, has resulted in increased resistance due to attendant reductions in the cross-sectional dimensions of certain conductive structures, as well as other factors. In t-type transistor 100, there are several components of body resistance: a) contact 5 resistance, b) resistance along the width of the transistor 100 under the gate structure 9, and c) pinch off resistance under the hammer head 10 along the boundary of the body tie implant from transistor S/D implant.
Of the three resistance components named above, the contact resistance is generally the smallest portion of the total resistance. The resistance along the width of the gate structure 9 is decreased somewhat by the halo implant 6, also known as pocket implants, which normally receives a dopant dose level about one order of magnitude greater than the well implant dose level. Well implant doses are trending downward in current manufacturing technology, which has led to an increase in resistance under the polysilicon hammer head 10 such that this resistance component has begun to dominate the body resistance.
In addition, resistance problems can be exacerbated by depletion phenomena, such as when source/drain extension depletion areas create a “pinch off” under the hammerhead 10, as shown in FIG. 3. FIG. 3 is an enlargement of a portion of the t-type transistor 100 of FIG. 1 near the hammer head 10. From FIG. 3, the depletion areas 13 near the hammer head 10 of S/D extensions have created a pinch off region 14 in the channel under the hammerhead 10, which results in increased resistance. This phenomenon is illustrated from another perspective in FIG. 4.
FIG. 4 illustrates a cross-sectional view of a portion 100 of a t-type transistor along the point indicated by Line B in FIG. 1. The pinch off region 14 as created by the overlapping depletion areas 13 is plainly seen. The gate width 7 is indicated by the dashed lines appearing in the hammerhead 10 cross section. Note that the two depletion areas do not need to overlap, as illustrated, to result in an increased resistance due to pinch off.
Therefore, a method which overcomes these problems and limitations would be useful.